Jan 20, 2024

TSMC tandem builds exotic new MRAM-based memory with radically lower latency and power consumption

Posted by in categories: computing, life extension

Data is written to the memory cell by changing the magnetization in the free layer (which acts as the ‘storage’ layer in the MRAM bit cell) by passing a current through the heavy metal layer, which generates a spin current and injects it into the adjacent magnetic layer, switching its orientation and thus changing its state. Reading data involves assessing the magnetoresistance of the MTJ by directing a current through the junction. The main difference between STT-and SOT-MRAM resides in the current injection geometry used for the write process, and apparently, the SOT method ensures lower power consumption and device longevity.

While SOT-MRAM offers lower standby power than SRAM, it needs high currents for write operations, so its dynamic power consumption is still quite high. Furthermore, SOT-SRAM cells are still larger than SRAM cells, and they are harder to make. As a result, while the SOT-SRAM technology looks promising, it is unlikely that it will replace SRAM any time soon. Yet, for in-memory computing applications, SOT-MRAM could make a lot of sense, if not now, but when TSMC learns how to make SOT-MRAM cost-efficiently.

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